Project Information c:\my documents\cs152a\lab6b\receivercntr.rpt MAX+plus II Compiler Report File Version 7.21 Student Edition Compiled: 12/08/00 10:05:35 Copyright (C) 1991-1997 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful Untitled ** DEVICE SUMMARY ** Chip/ Input Output Bidir Shareable POF Device Pins Pins Pins LCs Expanders % Utilized receivercntr EPM7128SLC84-7 6 13 0 13 7 10 % User Pins: 6 13 0 Project Information c:\my documents\cs152a\lab6b\receivercntr.rpt ** AUTO GLOBAL SIGNALS ** INFO: Signal 'Clock' chosen for auto global Clock Project Information c:\my documents\cs152a\lab6b\receivercntr.rpt ** STATE MACHINE ASSIGNMENTS ** SM: MACHINE OF BITS ( Q3, Q2, Q1, Q0 ) WITH STATES ( S0 = B"0000", S1 = B"0001", S2 = B"0010", S3 = B"0011", S4 = B"0100", S5 = B"0101", S6 = B"0110", S7 = B"0111", S8 = B"1000", S9 = B"1001", S10 = B"1010" ); Device-Specific Information: c:\my documents\cs152a\lab6b\receivercntr.rpt receivercntr ***** Logic for device 'receivercntr' compiled without errors. Device: EPM7128SLC84-7 Turbo: ON Security: OFF Device Options: Enable JTAG Support = ON JTAG User Code = ffff R e a d L C o y a c d l O C E O e u S r R R R n u C t e y S E E E c t o D S S p n p e S S S V r p m e t t u d t n E E E C C y u p V c a a t D D d R R R C l p t l C r t t A o o R G V V V I G G G o G t R e C y e e c n n e N E E E N N N N c N e e t I p R R k e e q D D D D T D D D k D r q e O t 2 3 -----------------------------------------------------------------_ / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | Reset | 12 74 | StateR1 VCCIO | 13 73 | StateR0 #TDI | 14 72 | GND RESERVED | 15 71 | #TDO RESERVED | 16 70 | RESERVED RESERVED | 17 69 | RESERVED RESERVED | 18 68 | SendUpper GND | 19 67 | SendLower RESERVED | 20 66 | VCCIO RESERVED | 21 65 | ShiftRegister RESERVED | 22 EPM7128SLC84-7 64 | ReadData #TMS | 23 63 | ReceiveAck RESERVED | 24 62 | #TCK RESERVED | 25 61 | RESERVED VCCIO | 26 60 | RESERVED RESERVED | 27 59 | GND RESERVED | 28 58 | RESERVED RESERVED | 29 57 | RESERVED RESERVED | 30 56 | RESERVED RESERVED | 31 55 | RESERVED GND | 32 54 | RESERVED |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _| ------------------------------------------------------------------ R R R R R V R R R G V R R R G R R R R R V E E E E E C E E E N C E E E N E E E E E C S S S S S C S S S D C S S S D S S S S S C E E E E E I E E E I E E E E E E E E I R R R R R O R R R N R R R R R R R R O V V V V V V V V T V V V V V V V V E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D N.C. = Not Connected. VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 or 5.0 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which will be tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary Scan Testing Pin. Device-Specific Information: c:\my documents\cs152a\lab6b\receivercntr.rpt receivercntr ** RESOURCE USAGE ** Shareable External Logic Array Block Logic Cells I/O Pins Expanders Interconnect A: LC1 - LC16 0/16( 0%) 5/ 8( 62%) 0/16( 0%) 0/36( 0%) B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) D: LC49 - LC64 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%) E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%) F: LC81 - LC96 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) G: LC97 - LC112 5/16( 31%) 6/ 8( 75%) 0/16( 0%) 4/36( 11%) H: LC113 - LC128 8/16( 50%) 8/ 8(100%) 7/16( 43%) 9/36( 25%) Total dedicated input pins used: 1/4 ( 25%) Total I/O pins used: 22/64 ( 34%) Total logic cells used: 13/128 ( 10%) Total shareable expanders used: 7/128 ( 5%) Total Turbo logic cells used: 13/128 ( 10%) Total shareable expanders not available (n/a): 0/128 ( 0%) Average fan-in: 5.15 Total fan-in: 67 Total input pins required: 6 Total input registers required: 0 Total output pins required: 13 Total bidirectional pins required: 0 Total reserved pins required 4 Total logic cells required: 13 Total flipflops required: 4 Total pterms required: 32 Total logic cells lending parallel expanders: 0 Total shareable expanders in database: 7 Synthesized logic cells: 0/ 128 ( 0%) Device-Specific Information: c:\my documents\cs152a\lab6b\receivercntr.rpt receivercntr ** INPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 83 - - INPUT 0 0 0 0 0 0 0 Clock 9 (8) (A) INPUT 0 0 0 0 0 1 0 CryptDone 11 (5) (A) INPUT 0 0 0 0 0 4 0 OutputAck 12 (3) (A) INPUT 0 0 0 0 0 4 0 Reset 10 (6) (A) INPUT 0 0 0 0 0 2 0 SendDone 8 (11) (A) INPUT 0 0 0 0 0 1 0 SendReq Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: c:\my documents\cs152a\lab6b\receivercntr.rpt receivercntr ** OUTPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 77 123 H OUTPUT t 0 0 0 0 4 0 0 Decrypt 81 128 H OUTPUT t 0 0 0 0 4 0 0 LoadEncrypter 80 126 H OUTPUT t 0 0 0 0 4 0 0 OutputReq 79 125 H OUTPUT t 0 0 0 0 4 0 0 ReadCycleComplete 64 99 G OUTPUT t 0 0 0 0 4 0 0 ReadData 63 97 G OUTPUT t 0 0 0 0 3 0 0 ReceiveAck 67 104 G OUTPUT t 0 0 0 0 4 0 0 SendLower 68 105 G OUTPUT t 0 0 0 0 4 0 0 SendUpper 65 101 G OUTPUT t 0 0 0 0 4 0 0 ShiftRegister 73 115 H FF + t 6 0 0 5 4 12 0 StateR0 74 117 H FF + t 1 0 0 2 4 13 0 StateR1 76 120 H FF + t 0 0 0 3 4 13 0 StateR2 75 118 H FF + t 0 0 0 2 4 13 0 StateR3 Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: c:\my documents\cs152a\lab6b\receivercntr.rpt receivercntr ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'G': Logic cells placed in LAB 'G' +--------- LC99 ReadData | +------- LC97 ReceiveAck | | +----- LC104 SendLower | | | +--- LC105 SendUpper | | | | +- LC101 ShiftRegister | | | | | | | | | | Other LABs fed by signals | | | | | that feed LAB 'G' LC | | | | | | A B C D E F G H | Logic cells that feed LAB 'G': Pin 83 -> - - - - - | - - - - - - - - | <-- Clock LC115-> * - * * * | - - - - - - * * | <-- StateR0 LC117-> * * * * * | - - - - - - * * | <-- StateR1 LC120-> * * * * * | - - - - - - * * | <-- StateR2 LC118-> * * * * * | - - - - - - * * | <-- StateR3 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: c:\my documents\cs152a\lab6b\receivercntr.rpt receivercntr ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'H': Logic cells placed in LAB 'H' +--------------- LC123 Decrypt | +------------- LC128 LoadEncrypter | | +----------- LC126 OutputReq | | | +--------- LC125 ReadCycleComplete | | | | +------- LC115 StateR0 | | | | | +----- LC117 StateR1 | | | | | | +--- LC120 StateR2 | | | | | | | +- LC118 StateR3 | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | that feed LAB 'H' LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H': LC115-> * * * * * * * * | - - - - - - * * | <-- StateR0 LC117-> * * * * * * * * | - - - - - - * * | <-- StateR1 LC120-> * * * * * * * * | - - - - - - * * | <-- StateR2 LC118-> * * * * * * * * | - - - - - - * * | <-- StateR3 Pin 83 -> - - - - - - - - | - - - - - - - - | <-- Clock 9 -> - - - - * - - - | - - - - - - - * | <-- CryptDone 11 -> - - - - * * * * | - - - - - - - * | <-- OutputAck 12 -> - - - - * * * * | - - - - - - - * | <-- Reset 10 -> - - - - * - * - | - - - - - - - * | <-- SendDone 8 -> - - - - * - - - | - - - - - - - * | <-- SendReq * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: c:\my documents\cs152a\lab6b\receivercntr.rpt receivercntr ** EQUATIONS ** Clock : INPUT; CryptDone : INPUT; OutputAck : INPUT; Reset : INPUT; SendDone : INPUT; SendReq : INPUT; -- Node name is 'Decrypt' -- Equation name is 'Decrypt', location is LC123, type is output. Decrypt = LCELL( _EQ001 $ GND); _EQ001 = !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is 'LoadEncrypter' -- Equation name is 'LoadEncrypter', location is LC128, type is output. LoadEncrypter = LCELL( _EQ002 $ GND); _EQ002 = StateR0 & !StateR1 & StateR2 & !StateR3; -- Node name is 'OutputReq' -- Equation name is 'OutputReq', location is LC126, type is output. OutputReq = LCELL( _EQ003 $ GND); _EQ003 = StateR0 & StateR1 & StateR2 & !StateR3 # StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'ReadCycleComplete' -- Equation name is 'ReadCycleComplete', location is LC125, type is output. ReadCycleComplete = LCELL( _EQ004 $ GND); _EQ004 = !StateR0 & !StateR1 & StateR2 & !StateR3; -- Node name is 'ReadData' -- Equation name is 'ReadData', location is LC099, type is output. ReadData = LCELL( _EQ005 $ GND); _EQ005 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is 'ReceiveAck' -- Equation name is 'ReceiveAck', location is LC097, type is output. ReceiveAck = LCELL( _EQ006 $ GND); _EQ006 = StateR1 & !StateR2 & !StateR3; -- Node name is 'SendLower' -- Equation name is 'SendLower', location is LC104, type is output. SendLower = LCELL( _EQ007 $ GND); _EQ007 = StateR0 & StateR1 & StateR2 & !StateR3 # !StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'SendUpper' -- Equation name is 'SendUpper', location is LC105, type is output. SendUpper = LCELL( _EQ008 $ GND); _EQ008 = !StateR0 & StateR1 & !StateR2 & StateR3 # StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'ShiftRegister' -- Equation name is 'ShiftRegister', location is LC101, type is output. ShiftRegister = LCELL( _EQ009 $ GND); _EQ009 = StateR0 & StateR1 & !StateR2 & !StateR3; -- Node name is 'StateR0' = 'Q0' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR0', location is LC115, type is output. StateR0 = DFFE( _EQ010 $ VCC, GLOBAL( Clock), !Reset, VCC, VCC); _EQ010 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006; _X001 = EXP( CryptDone & !StateR0 & StateR1 & StateR2 & !StateR3); _X002 = EXP(!OutputAck & StateR0 & StateR1 & StateR2 & !StateR3); _X003 = EXP( SendDone & !StateR0 & !StateR1 & StateR2 & !StateR3); _X004 = EXP(!SendReq & !StateR0 & StateR1 & !StateR2 & !StateR3); _X005 = EXP( SendReq & !StateR0 & !StateR1 & !StateR2 & !StateR3); _X006 = EXP(!OutputAck & !StateR1 & !StateR2 & StateR3); -- Node name is 'StateR1' = 'Q1' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR1', location is LC117, type is output. StateR1 = TFFE( _EQ011, GLOBAL( Clock), !Reset, VCC, VCC); _EQ011 = !OutputAck & !StateR0 & StateR1 & !StateR2 & StateR3 # OutputAck & StateR0 & !StateR1 & !StateR2 # StateR0 & !StateR3 & _X007; _X007 = EXP(!OutputAck & StateR1 & StateR2); -- Node name is 'StateR2' = 'Q2' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR2', location is LC120, type is output. StateR2 = TFFE( _EQ012, GLOBAL( Clock), !Reset, VCC, VCC); _EQ012 = !SendDone & !StateR0 & !StateR1 & StateR2 & !StateR3 # OutputAck & StateR0 & StateR1 & !StateR3 # StateR0 & StateR1 & !StateR2 & !StateR3; -- Node name is 'StateR3' = 'Q3' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR3', location is LC118, type is output. StateR3 = TFFE( _EQ013, GLOBAL( Clock), !Reset, VCC, VCC); _EQ013 = OutputAck & StateR0 & StateR1 & StateR2 & !StateR3 # !OutputAck & !StateR0 & StateR1 & !StateR2 & StateR3; -- Shareable expanders that are duplicated in multiple LABs: -- (none) Project Information c:\my documents\cs152a\lab6b\receivercntr.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Standard Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'MAX7000S' family DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on PARALLEL_EXPANDERS = off REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SOFT_BUFFER_INSERTION = on SUBFACTOR_EXTRACTION = on TURBO_BIT = on XOR_SYNTHESIS = on IGNORE_SOFT_BUFFERS = off USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic I/O Cell Registers = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off One-Hot State Machine Encoding = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = on Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interface Menu Commands ----------------------- EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:00 Logic Synthesizer 00:00:00 Partitioner 00:00:00 Fitter 00:00:00 Timing SNF Extractor 00:00:01 Assembler 00:00:00 -------------------------- -------- Total Time 00:00:01 Memory Allocated ----------------- Peak memory allocated during compilation = 4,036K