Project Information d:\lab6b\receiver.rpt MAX+plus II Compiler Report File Version 9.23 3/19/99 Compiled: 12/08/2000 16:18:41 Copyright (C) 1988-1999 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir Shareable POF Device Pins Pins Pins LCs Expanders % Utilized receiver EPM7128SLC84-7 8 10 0 66 33 51 % User Pins: 8 10 0 Project Information d:\lab6b\receiver.rpt ** PROJECT COMPILATION MESSAGES ** Warning: GLOBAL primitive on node 'Clock' feeds logic -- non-global signal usage may result Warning: Ignored unnecessary INPUT pin 'Encrypt3' Project Information d:\lab6b\receiver.rpt ** AUTO GLOBAL SIGNALS ** INFO: Signal 'Clock' chosen for auto global Clock Project Information d:\lab6b\receiver.rpt ** STATE MACHINE ASSIGNMENTS ** |receivercntr:34|SM: MACHINE OF BITS ( |receivercntr:34|Q3, |receivercntr:34|Q2, |receivercntr:34|Q1, |receivercntr:34|Q0 ) WITH STATES ( S0 = B"0000", S1 = B"0001", S2 = B"0010", S3 = B"0011", S4 = B"0100", S5 = B"0101", S6 = B"0110", S7 = B"0111", S8 = B"1000", S9 = B"1001", S10 = B"1010" ); Project Information d:\lab6b\receiver.rpt ** FILE HIERARCHY ** |crypter:2| |crypter:2|74198:52| |crypter:2|74162:37| |74198:6| |74393:7| |74157:10| |receivercntr:34| Device-Specific Information: d:\lab6b\receiver.rpt receiver ***** Logic for device 'receiver' compiled without errors. Device: EPM7128SLC84-7 Device Options: Turbo Bit = ON Security Bit = OFF Enable JTAG Support = ON User Code = ffff MultiVolt I/O = OFF O E E E u R R R R R R n n n t S E E E E E E c c c p e V S S S S S S r r r u n R C C E E E V E E E y y y t d D e C l R R R C R R R p p p A G R a s I G G G o G V V V C V V V t t t c N e t e N N N N c N E E E I E E E 2 1 0 k D q a t T D D D k D D D D O D D D -----------------------------------------------------------------_ / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | RESERVED | 12 74 | OutputReq VCCIO | 13 73 | Out3 #TDI | 14 72 | GND RESERVED | 15 71 | #TDO RESERVED | 16 70 | RESERVED RESERVED | 17 69 | RESERVED RESERVED | 18 68 | RESERVED GND | 19 67 | RESERVED RESERVED | 20 66 | VCCIO RESERVED | 21 65 | RESERVED RESERVED | 22 EPM7128SLC84-7 64 | RESERVED #TMS | 23 63 | Out1 RESERVED | 24 62 | #TCK RESERVED | 25 61 | RESERVED VCCIO | 26 60 | RESERVED RESERVED | 27 59 | GND RESERVED | 28 58 | RESERVED RESERVED | 29 57 | RESERVED RESERVED | 30 56 | RESERVED RESERVED | 31 55 | RESERVED GND | 32 54 | RESERVED |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _| ------------------------------------------------------------------ R R R R R V O S O G V R R S G S R R S R V E E E E E C u t u N C e E t N t E E t E C S S S S S C t a t D C c S a D a S S a S C E E E E E I 0 t 2 I e E t t E E t E I R R R R R O e N i R e e R R e R O V V V V V R T v V R R V V R V E E E E E 2 e E 0 1 E E 3 E D D D D D A D D D D c k N.C. = No Connect, This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information: d:\lab6b\receiver.rpt receiver ** RESOURCE USAGE ** Shareable External Logic Array Block Logic Cells I/O Pins Expanders Interconnect A: LC1 - LC16 0/16( 0%) 7/ 8( 87%) 0/16( 0%) 0/36( 0%) B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) D: LC49 - LC64 8/16( 50%) 3/ 8( 37%) 6/16( 37%) 15/36( 41%) E: LC65 - LC80 10/16( 62%) 4/ 8( 50%) 15/16( 93%) 21/36( 58%) F: LC81 - LC96 16/16(100%) 1/ 8( 12%) 16/16(100%) 32/36( 88%) G: LC97 - LC112 16/16(100%) 2/ 8( 25%) 16/16(100%) 32/36( 88%) H: LC113 - LC128 16/16(100%) 2/ 8( 25%) 16/16(100%) 27/36( 75%) Total dedicated input pins used: 1/4 ( 25%) Total I/O pins used: 21/64 ( 32%) Total logic cells used: 66/128 ( 51%) Total shareable expanders used: 33/128 ( 25%) Total Turbo logic cells used: 66/128 ( 51%) Total shareable expanders not available (n/a): 36/128 ( 28%) Average fan-in: 9.96 Total fan-in: 658 Total input pins required: 8 Total fast input logic cells required: 0 Total output pins required: 10 Total bidirectional pins required: 0 Total reserved pins required 4 Total logic cells required: 66 Total flipflops required: 29 Total product terms required: 302 Total logic cells lending parallel expanders: 0 Total shareable expanders in database: 27 Synthesized logic cells: 31/ 128 ( 24%) Device-Specific Information: d:\lab6b\receiver.rpt receiver ** INPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 83 - - INPUT G 0 0 0 0 0 0 13 Clock 5 (14) (A) INPUT 0 0 0 0 0 0 1 Data 9 (8) (A) INPUT 0 0 0 0 0 0 35 Encrypt0 10 (6) (A) INPUT 0 0 0 0 0 0 34 Encrypt1 11 (5) (A) INPUT 0 0 0 0 0 0 26 Encrypt2 8 (11) (A) INPUT 0 0 0 0 0 3 1 OutputAck 4 (16) (A) INPUT 0 0 0 0 0 4 12 Reset 6 (13) (A) INPUT 0 0 0 0 0 0 1 SendReq Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell G = Global Source. Fan-out destinations counted here do not include destinations that are driven using global routing resources. Refer to the Auto Global Signals, Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals Sections of this Report File for information on which signals' fan-outs are used as Clock, Clear, Preset, Output Enable, and synchronous Load signals. Device-Specific Information: d:\lab6b\receiver.rpt receiver ** OUTPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 74 117 H OUTPUT t 0 0 0 0 4 0 0 OutputReq 39 53 D OUTPUT t 1 0 1 0 6 0 0 Out0 63 97 G OUTPUT t 1 0 1 0 6 0 0 Out1 41 49 D OUTPUT t 1 0 1 0 6 0 0 Out2 73 115 H OUTPUT t 1 0 1 0 6 0 0 Out3 44 65 E OUTPUT t 0 0 0 0 3 0 0 ReceiveAck 46 69 E FF + t 0 0 0 1 3 8 54 StateR0 48 72 E FF + t 1 0 0 2 4 9 55 StateR1 40 51 D FF + t 1 0 0 2 7 9 53 StateR2 51 77 E FF + t 0 0 0 2 4 9 53 StateR3 Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: d:\lab6b\receiver.rpt receiver ** BURIED LOGIC ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name - 71 E DFFE t 5 1 1 4 9 0 24 |crypter:2|:1 - 113 H SOFT s t 1 0 1 3 7 1 5 |crypter:2|~3~1 - 114 H SOFT s t 0 0 0 3 8 1 5 |crypter:2|~3~2 (58) 91 F SOFT s t 1 0 1 3 4 0 8 |crypter:2|~20~1 - 90 F SOFT s t 1 0 1 3 6 0 8 |crypter:2|~20~2 - 116 H SOFT s t 1 0 1 3 8 0 1 |crypter:2|74162:37|~39~1 - 87 F SOFT s t 1 0 1 3 4 0 1 |crypter:2|74162:37|~42~1 - 70 E DFFE t 3 1 0 2 9 0 35 |crypter:2|74162:37|QA (|crypter:2|74162:37|:43) - 68 E DFFE t 5 1 0 4 11 0 34 |crypter:2|74162:37|QB (|crypter:2|74162:37|:44) - 66 E DFFE t 3 1 1 4 10 0 26 |crypter:2|74162:37|QC (|crypter:2|74162:37|:45) - 79 E DFFE t 2 1 0 4 12 0 2 |crypter:2|74162:37|QD (|crypter:2|74162:37|:46) - 122 H DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QA (|crypter:2|74198:52|:113) - 111 G DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QB (|crypter:2|74198:52|:114) (65) 101 G DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QC (|crypter:2|74198:52|:115) - 82 F DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QD (|crypter:2|74198:52|:116) - 81 F DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QE (|crypter:2|74198:52|:117) - 108 G DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QF (|crypter:2|74198:52|:118) - 92 F DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QG (|crypter:2|74198:52|:119) - 121 H DFFE t 4 3 0 1 12 1 7 |crypter:2|74198:52|QH (|crypter:2|74198:52|:120) (81) 128 H SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~121~1 - 127 H SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~121~2 (80) 126 H SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~121~3 (79) 125 H SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~122~1 - 102 G SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~122~2 - 100 G SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~122~3 (64) 99 G SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~123~1 - 98 G SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~123~2 (71) 112 G SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~123~3 (54) 83 F SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~124~1 (62) 96 F SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~124~2 - 95 F SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~124~3 (75) 118 H SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~125~1 - 84 F SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~125~2 (57) 88 F SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~125~3 - 110 G SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~126~1 - 103 G SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~126~2 (69) 107 G SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~126~3 (67) 104 G SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~127~1 (55) 85 F SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~127~2 (56) 86 F SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~127~3 - 124 H SOFT s t 1 0 1 3 8 0 1 |crypter:2|74198:52|~128~1 - 119 H SOFT s t 1 0 1 3 10 0 1 |crypter:2|74198:52|~128~2 (77) 123 H SOFT s t 1 0 1 2 9 0 1 |crypter:2|74198:52|~128~3 - 50 D SOFT s t 1 0 1 2 7 1 0 |receivercntr:34|Q0~1 (70) 109 G DFFE t 0 0 0 1 5 0 1 |74198:6|QA (|74198:6|:113) - 106 G DFFE t 0 0 0 1 5 0 2 |74198:6|QB (|74198:6|:114) (61) 94 F DFFE t 0 0 0 1 5 0 2 |74198:6|QC (|74198:6|:115) (60) 93 F DFFE t 0 0 0 1 5 0 2 |74198:6|QD (|74198:6|:116) (68) 105 G DFFE t 0 0 0 1 5 0 2 |74198:6|QE (|74198:6|:117) - 89 F DFFE t 0 0 0 1 5 0 2 |74198:6|QF (|74198:6|:118) (76) 120 H DFFE t 0 0 0 1 5 0 2 |74198:6|QG (|74198:6|:119) (49) 73 E DFFE t 0 0 0 2 4 0 2 |74198:6|QH (|74198:6|:120) (36) 57 D TFFE t 2 2 0 1 5 1 4 |74393:7|Q1A (|74393:7|:1) - 55 D TFFE t 2 2 0 1 6 1 3 |74393:7|Q1B (|74393:7|:3) - 54 D TFFE t 2 2 0 1 7 1 2 |74393:7|Q1C (|74393:7|:5) - 52 D TFFE t 2 2 0 1 8 0 4 |74393:7|Q1D (|74393:7|:9) Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: d:\lab6b\receiver.rpt receiver ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'D': Logic cells placed in LAB 'D' +--------------- LC53 Out0 | +------------- LC49 Out2 | | +----------- LC50 |receivercntr:34|Q0~1 | | | +--------- LC51 StateR2 | | | | +------- LC57 |74393:7|Q1A | | | | | +----- LC55 |74393:7|Q1B | | | | | | +--- LC54 |74393:7|Q1C | | | | | | | +- LC52 |74393:7|Q1D | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | that feed LAB 'D' LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D': LC51 -> * * * * * * * * | - - - * * * * * | <-- StateR2 LC57 -> - - * * * * * * | - - - * - - - - | <-- |74393:7|Q1A LC55 -> - - * * - * * * | - - - * - - - - | <-- |74393:7|Q1B LC54 -> - - * * - - * * | - - - * - - - - | <-- |74393:7|Q1C LC52 -> - - - - * * * * | - - - * - - - - | <-- |74393:7|Q1D Pin 83 -> - - - - - - - - | - - - - * * * * | <-- Clock 8 -> - - * * - - - - | - - - * * - - - | <-- OutputAck 4 -> - - - * * * * * | - - - * * * * * | <-- Reset 6 -> - - * - - - - - | - - - * - - - - | <-- SendReq LC111-> - * - - - - - - | - - - * - - * * | <-- |crypter:2|74198:52|QB LC82 -> * - - - - - - - | - - - * - * * - | <-- |crypter:2|74198:52|QD LC108-> - * - - - - - - | - - - * - * * - | <-- |crypter:2|74198:52|QF LC121-> * - - - - - - - | - - - * - * - * | <-- |crypter:2|74198:52|QH LC69 -> * * * * * * * * | - - - * * * * * | <-- StateR0 LC72 -> * * * * * * * * | - - - * * * * * | <-- StateR1 LC77 -> * * * * * * * * | - - - * * * * * | <-- StateR3 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\lab6b\receiver.rpt receiver ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'E': Logic cells placed in LAB 'E' +------------------- LC71 |crypter:2|:1 | +----------------- LC70 |crypter:2|74162:37|QA | | +--------------- LC68 |crypter:2|74162:37|QB | | | +------------- LC66 |crypter:2|74162:37|QC | | | | +----------- LC79 |crypter:2|74162:37|QD | | | | | +--------- LC65 ReceiveAck | | | | | | +------- LC69 StateR0 | | | | | | | +----- LC72 StateR1 | | | | | | | | +--- LC77 StateR3 | | | | | | | | | +- LC73 |74198:6|QH | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | that feed LAB 'E' LC | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E': LC71 -> - * * * * - - - - - | - - - - * * * * | <-- |crypter:2|:1 LC70 -> * * * * * - - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QA LC68 -> * - * * * - - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QB LC66 -> * - * * * - - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QC LC79 -> - - * - * - - - - - | - - - - * - - - | <-- |crypter:2|74162:37|QD LC69 -> * * * * * - - * * * | - - - * * * * * | <-- StateR0 LC72 -> * * * * * * - * * * | - - - * * * * * | <-- StateR1 LC77 -> * * * * * * - * * * | - - - * * * * * | <-- StateR3 Pin 83 -> * * * * * - - - - - | - - - - * * * * | <-- Clock 5 -> - - - - - - - - - * | - - - - * - - - | <-- Data 9 -> * * * * * - - - - - | - - - - * * * * | <-- Encrypt0 10 -> * - * * * - - - - - | - - - - * * * * | <-- Encrypt1 11 -> * - * * * - - - - - | - - - - * * * * | <-- Encrypt2 8 -> - - - - - - - * * - | - - - * * - - - | <-- OutputAck 4 -> - - - - - - * * * * | - - - * * * * * | <-- Reset LC113-> * * * * * - * - - - | - - - - * - - - | <-- |crypter:2|~3~1 LC114-> * * * * * - * - - - | - - - - * - - - | <-- |crypter:2|~3~2 LC116-> - * - - - - - - - - | - - - - * - - - | <-- |crypter:2|74162:37|~39~1 LC87 -> - - - - * - - - - - | - - - - * - - - | <-- |crypter:2|74162:37|~42~1 LC50 -> - - - - - - * - - - | - - - - * - - - | <-- |receivercntr:34|Q0~1 LC51 -> * * * * * * - * * * | - - - * * * * * | <-- StateR2 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\lab6b\receiver.rpt receiver ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'F': Logic cells placed in LAB 'F' +------------------------------- LC91 |crypter:2|~20~1 | +----------------------------- LC90 |crypter:2|~20~2 | | +--------------------------- LC87 |crypter:2|74162:37|~42~1 | | | +------------------------- LC82 |crypter:2|74198:52|QD | | | | +----------------------- LC81 |crypter:2|74198:52|QE | | | | | +--------------------- LC92 |crypter:2|74198:52|QG | | | | | | +------------------- LC83 |crypter:2|74198:52|~124~1 | | | | | | | +----------------- LC96 |crypter:2|74198:52|~124~2 | | | | | | | | +--------------- LC95 |crypter:2|74198:52|~124~3 | | | | | | | | | +------------- LC84 |crypter:2|74198:52|~125~2 | | | | | | | | | | +----------- LC88 |crypter:2|74198:52|~125~3 | | | | | | | | | | | +--------- LC85 |crypter:2|74198:52|~127~2 | | | | | | | | | | | | +------- LC86 |crypter:2|74198:52|~127~3 | | | | | | | | | | | | | +----- LC94 |74198:6|QC | | | | | | | | | | | | | | +--- LC93 |74198:6|QD | | | | | | | | | | | | | | | +- LC89 |74198:6|QF | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'F' LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F': LC91 -> - - - * * * - - - - - - - - - - | - - - - - * * * | <-- |crypter:2|~20~1 LC90 -> - - - * * * - - - - - - - - - - | - - - - - * * * | <-- |crypter:2|~20~2 LC82 -> - - - * - - * * * - - - - - - - | - - - * - * * - | <-- |crypter:2|74198:52|QD LC81 -> - - - * * - - * * * * - - - - - | - - - - - * - * | <-- |crypter:2|74198:52|QE LC92 -> - - - - - * - - - - - * * - - - | - - - - - * * - | <-- |crypter:2|74198:52|QG LC83 -> - - - * - - - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~124~1 LC96 -> - - - * - - - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~124~2 LC95 -> - - - * - - - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~124~3 LC84 -> - - - - * - - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~125~2 LC88 -> - - - - * - - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~125~3 LC85 -> - - - - - * - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~127~2 LC86 -> - - - - - * - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~127~3 LC93 -> - - - * - - - - - - - - - * - - | - - - - - * - - | <-- |74198:6|QD Pin 83 -> - - - * * * - - - - - - - - - - | - - - - * * * * | <-- Clock 9 -> * * * - - - * * * * * * * - - - | - - - - * * * * | <-- Encrypt0 10 -> * * * - - - * * * * * * * - - - | - - - - * * * * | <-- Encrypt1 11 -> * * * - - - * * - * - * - - - - | - - - - * * * * | <-- Encrypt2 4 -> - - - - - - - - - - - - - * * * | - - - * * * * * | <-- Reset LC71 -> - * * - - - - * * * * * * - - - | - - - - * * * * | <-- |crypter:2|:1 LC70 -> * * * - - - * * * * * * * - - - | - - - - * * * * | <-- |crypter:2|74162:37|QA LC68 -> * * * - - - * * * * * * * - - - | - - - - * * * * | <-- |crypter:2|74162:37|QB LC66 -> * * * - - - * * - * - * - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QC LC108-> - - - - * - - - - * * - - - - - | - - - * - * * - | <-- |crypter:2|74198:52|QF LC121-> - - - - - * - - - - - * * - - - | - - - * - * - * | <-- |crypter:2|74198:52|QH LC118-> - - - - * - - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~125~1 LC104-> - - - - - * - - - - - - - - - - | - - - - - * - - | <-- |crypter:2|74198:52|~127~1 LC69 -> - * - * * * * * * * * * * * * * | - - - * * * * * | <-- StateR0 LC72 -> * * - * * * * * * * * * * * * * | - - - * * * * * | <-- StateR1 LC51 -> - - - * * * * * * * * * * * * * | - - - * * * * * | <-- StateR2 LC77 -> - - - * * * * * * * * * * * * * | - - - * * * * * | <-- StateR3 LC105-> - - - - * - - - - - - - - - * - | - - - - - * - - | <-- |74198:6|QE LC120-> - - - - - * - - - - - - - - - * | - - - - - * - - | <-- |74198:6|QG * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\lab6b\receiver.rpt receiver ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'G': Logic cells placed in LAB 'G' +------------------------------- LC111 |crypter:2|74198:52|QB | +----------------------------- LC101 |crypter:2|74198:52|QC | | +--------------------------- LC108 |crypter:2|74198:52|QF | | | +------------------------- LC102 |crypter:2|74198:52|~122~2 | | | | +----------------------- LC100 |crypter:2|74198:52|~122~3 | | | | | +--------------------- LC99 |crypter:2|74198:52|~123~1 | | | | | | +------------------- LC98 |crypter:2|74198:52|~123~2 | | | | | | | +----------------- LC112 |crypter:2|74198:52|~123~3 | | | | | | | | +--------------- LC110 |crypter:2|74198:52|~126~1 | | | | | | | | | +------------- LC103 |crypter:2|74198:52|~126~2 | | | | | | | | | | +----------- LC107 |crypter:2|74198:52|~126~3 | | | | | | | | | | | +--------- LC104 |crypter:2|74198:52|~127~1 | | | | | | | | | | | | +------- LC97 Out1 | | | | | | | | | | | | | +----- LC109 |74198:6|QA | | | | | | | | | | | | | | +--- LC106 |74198:6|QB | | | | | | | | | | | | | | | +- LC105 |74198:6|QE | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'G' LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G': LC111-> * - - * * - - - - - - - - - - - | - - - * - - * * | <-- |crypter:2|74198:52|QB LC101-> * * - * * * * * - - - - * - - - | - - - - - - * - | <-- |crypter:2|74198:52|QC LC108-> - - * - - - - - * * * - - - - - | - - - * - * * - | <-- |crypter:2|74198:52|QF LC102-> * - - - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~122~2 LC100-> * - - - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~122~3 LC99 -> - * - - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~123~1 LC98 -> - * - - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~123~2 LC112-> - * - - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~123~3 LC110-> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~126~1 LC103-> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~126~2 LC107-> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~126~3 LC106-> * - - - - - - - - - - - - * - - | - - - - - - * - | <-- |74198:6|QB Pin 83 -> * * * - - - - - - - - - - - - - | - - - - * * * * | <-- Clock 9 -> - - - * * * * * * * * * - - - - | - - - - * * * * | <-- Encrypt0 10 -> - - - * * * * * * * * * - - - - | - - - - * * * * | <-- Encrypt1 11 -> - - - * - * * - * * - * - - - - | - - - - * * * * | <-- Encrypt2 4 -> - - - - - - - - - - - - - * * * | - - - * * * * * | <-- Reset LC71 -> - - - * * - * * - * * - - - - - | - - - - * * * * | <-- |crypter:2|:1 LC91 -> * * * - - - - - - - - - - - - - | - - - - - * * * | <-- |crypter:2|~20~1 LC90 -> * * * - - - - - - - - - - - - - | - - - - - * * * | <-- |crypter:2|~20~2 LC70 -> - - - * * * * * * * * * - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QA LC68 -> - - - * * * * * * * * * - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QB LC66 -> - - - * - * * - * * - * - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QC LC82 -> - * - - - - * * - - - - - - - - | - - - * - * * - | <-- |crypter:2|74198:52|QD LC92 -> - - * - - - - - - * * * * - - - | - - - - - * * - | <-- |crypter:2|74198:52|QG LC125-> * - - - - - - - - - - - - - - - | - - - - - - * - | <-- |crypter:2|74198:52|~122~1 LC69 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR0 LC72 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR1 LC51 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR2 LC77 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR3 LC94 -> - * - - - - - - - - - - - - * - | - - - - - - * - | <-- |74198:6|QC LC89 -> - - * - - - - - - - - - - - - * | - - - - - - * - | <-- |74198:6|QF * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\lab6b\receiver.rpt receiver ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'H': Logic cells placed in LAB 'H' +------------------------------- LC113 |crypter:2|~3~1 | +----------------------------- LC114 |crypter:2|~3~2 | | +--------------------------- LC116 |crypter:2|74162:37|~39~1 | | | +------------------------- LC122 |crypter:2|74198:52|QA | | | | +----------------------- LC121 |crypter:2|74198:52|QH | | | | | +--------------------- LC128 |crypter:2|74198:52|~121~1 | | | | | | +------------------- LC127 |crypter:2|74198:52|~121~2 | | | | | | | +----------------- LC126 |crypter:2|74198:52|~121~3 | | | | | | | | +--------------- LC125 |crypter:2|74198:52|~122~1 | | | | | | | | | +------------- LC118 |crypter:2|74198:52|~125~1 | | | | | | | | | | +----------- LC124 |crypter:2|74198:52|~128~1 | | | | | | | | | | | +--------- LC119 |crypter:2|74198:52|~128~2 | | | | | | | | | | | | +------- LC123 |crypter:2|74198:52|~128~3 | | | | | | | | | | | | | +----- LC117 OutputReq | | | | | | | | | | | | | | +--- LC115 Out3 | | | | | | | | | | | | | | | +- LC120 |74198:6|QG | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'H' LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H': LC122-> - - - * * * * * - - - * * - * - | - - - - - - - * | <-- |crypter:2|74198:52|QA LC121-> - - - - * - - - - - * * * - - - | - - - * - * - * | <-- |crypter:2|74198:52|QH LC128-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |crypter:2|74198:52|~121~1 LC127-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |crypter:2|74198:52|~121~2 LC126-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |crypter:2|74198:52|~121~3 LC124-> - - - - * - - - - - - - - - - - | - - - - - - - * | <-- |crypter:2|74198:52|~128~1 LC119-> - - - - * - - - - - - - - - - - | - - - - - - - * | <-- |crypter:2|74198:52|~128~2 LC123-> - - - - * - - - - - - - - - - - | - - - - - - - * | <-- |crypter:2|74198:52|~128~3 Pin 83 -> - - - * * - - - - - - - - - - - | - - - - * * * * | <-- Clock 9 -> * * * - - * * * * * * * * - - - | - - - - * * * * | <-- Encrypt0 10 -> * * * - - * * * * * * * * - - - | - - - - * * * * | <-- Encrypt1 11 -> * * * - - * * - * * * * - - - - | - - - - * * * * | <-- Encrypt2 4 -> - - - - - - - - - - - - - - - * | - - - * * * * * | <-- Reset LC71 -> - * * - - - * * - - - * * - - - | - - - - * * * * | <-- |crypter:2|:1 LC91 -> - - - * * - - - - - - - - - - - | - - - - - * * * | <-- |crypter:2|~20~1 LC90 -> - - - * * - - - - - - - - - - - | - - - - - * * * | <-- |crypter:2|~20~2 LC70 -> * * * - - * * * * * * * * - - - | - - - - * * * * | <-- |crypter:2|74162:37|QA LC68 -> * * * - - * * * * * * * * - - - | - - - - * * * * | <-- |crypter:2|74162:37|QB LC66 -> * * * - - * * - * * * * - - - - | - - - - * * * * | <-- |crypter:2|74162:37|QC LC111-> - - - * - - * * * - - - - - - - | - - - * - - * * | <-- |crypter:2|74198:52|QB LC81 -> - - - - - - - - - * - - - - * - | - - - - - * - * | <-- |crypter:2|74198:52|QE LC69 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR0 LC72 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR1 LC51 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR2 LC77 -> * * * * * * * * * * * * * * * * | - - - * * * * * | <-- StateR3 LC109-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |74198:6|QA LC73 -> - - - - * - - - - - - - - - - * | - - - - - - - * | <-- |74198:6|QH * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\lab6b\receiver.rpt receiver ** EQUATIONS ** Clock : INPUT; Data : INPUT; Encrypt0 : INPUT; Encrypt1 : INPUT; Encrypt2 : INPUT; OutputAck : INPUT; Reset : INPUT; SendReq : INPUT; -- Node name is 'OutputReq' -- Equation name is 'OutputReq', location is LC117, type is output. OutputReq = LCELL( _EQ001 $ GND); _EQ001 = StateR0 & StateR1 & StateR2 & !StateR3 # StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'Out0' -- Equation name is 'Out0', location is LC053, type is output. Out0 = LCELL( _EQ002 $ _LC082); _EQ002 = !_LC082 & _LC121 & StateR0 & StateR1 & StateR2 & !StateR3 # _LC082 & !_LC121 & StateR0 & StateR1 & StateR2 & !StateR3 # !_LC082 & _LC121 & !StateR0 & !StateR1 & !StateR2 & StateR3 # _LC082 & !_LC121 & !StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'Out1' -- Equation name is 'Out1', location is LC097, type is output. Out1 = LCELL( _EQ003 $ _LC101); _EQ003 = _LC092 & !_LC101 & StateR0 & StateR1 & StateR2 & !StateR3 # !_LC092 & _LC101 & StateR0 & StateR1 & StateR2 & !StateR3 # _LC092 & !_LC101 & !StateR0 & !StateR1 & !StateR2 & StateR3 # !_LC092 & _LC101 & !StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'Out2' -- Equation name is 'Out2', location is LC049, type is output. Out2 = LCELL( _EQ004 $ _LC111); _EQ004 = _LC108 & !_LC111 & StateR0 & StateR1 & StateR2 & !StateR3 # !_LC108 & _LC111 & StateR0 & StateR1 & StateR2 & !StateR3 # _LC108 & !_LC111 & !StateR0 & !StateR1 & !StateR2 & StateR3 # !_LC108 & _LC111 & !StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'Out3' -- Equation name is 'Out3', location is LC115, type is output. Out3 = LCELL( _EQ005 $ _LC122); _EQ005 = _LC081 & !_LC122 & StateR0 & StateR1 & StateR2 & !StateR3 # !_LC081 & _LC122 & StateR0 & StateR1 & StateR2 & !StateR3 # _LC081 & !_LC122 & !StateR0 & !StateR1 & !StateR2 & StateR3 # !_LC081 & _LC122 & !StateR0 & !StateR1 & !StateR2 & StateR3; -- Node name is 'ReceiveAck' -- Equation name is 'ReceiveAck', location is LC065, type is output. ReceiveAck = LCELL( _EQ006 $ GND); _EQ006 = StateR1 & !StateR2 & !StateR3; -- Node name is 'StateR0' = '|receivercntr:34|Q0' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR0', type is output StateR0 = DFFE( _EQ007 $ VCC, GLOBAL( Clock), !Reset, VCC, VCC); _EQ007 = !_LC050 & !_LC113 & !_LC114; -- Node name is 'StateR1' = '|receivercntr:34|Q1' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR1', type is output StateR1 = TFFE( _EQ008, GLOBAL( Clock), !Reset, VCC, VCC); _EQ008 = !OutputAck & !StateR0 & StateR1 & !StateR2 & StateR3 # OutputAck & StateR0 & !StateR1 & !StateR2 # StateR0 & !StateR3 & _X001; _X001 = EXP(!OutputAck & StateR1 & StateR2); -- Node name is 'StateR2' = '|receivercntr:34|Q2' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR2', type is output StateR2 = TFFE( _EQ009, GLOBAL( Clock), !Reset, VCC, VCC); _EQ009 = OutputAck & StateR0 & StateR1 & StateR2 & !StateR3 # !StateR0 & !StateR1 & StateR2 & !StateR3 & _X002 # StateR0 & StateR1 & !StateR2 & !StateR3; _X002 = EXP(!_LC054 & !_LC055 & !_LC057); -- Node name is 'StateR3' = '|receivercntr:34|Q3' from file "receivercntr.tdf" line 9, column 24 -- Equation name is 'StateR3', type is output StateR3 = TFFE( _EQ010, GLOBAL( Clock), !Reset, VCC, VCC); _EQ010 = OutputAck & StateR0 & StateR1 & StateR2 & !StateR3 # !OutputAck & !StateR0 & StateR1 & !StateR2 & StateR3; -- Node name is '|crypter:2|:1' -- Equation name is '_LC071', type is buried _LC071 = DFFE( _EQ011 $ _EQ012, _EQ013, VCC, VCC, VCC); _EQ011 = Encrypt0 & !_LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 & _X003 & _X004 & _X005 # !Encrypt0 & _LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 & _X003 & _X004 & _X005 # Encrypt1 & !_LC068 & !StateR0 & StateR1 & StateR2 & !StateR3 & _X003 & _X004 & _X005; _X003 = EXP(!Encrypt2 & _LC066); _X004 = EXP(!Encrypt1 & _LC068); _X005 = EXP( Encrypt2 & !_LC066); _EQ012 = !StateR0 & StateR1 & StateR2 & !StateR3 & _X003 & _X004 & _X005; _X003 = EXP(!Encrypt2 & _LC066); _X004 = EXP(!Encrypt1 & _LC068); _X005 = EXP( Encrypt2 & !_LC066); _EQ013 = !_LC113 & !_LC114 & _X006; _X006 = EXP(!Clock & !StateR0 & StateR1 & StateR2 & !StateR3); -- Node name is '|crypter:2|~3~1' -- Equation name is '_LC113', type is buried -- synthesized logic cell _LC113 = LCELL( _EQ014 $ GND); _EQ014 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|~3~2' -- Equation name is '_LC114', type is buried -- synthesized logic cell _LC114 = LCELL( _EQ015 $ GND); _EQ015 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|~20~1' -- Equation name is '_LC091', type is buried -- synthesized logic cell _LC091 = LCELL( _EQ016 $ GND); _EQ016 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & StateR1 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & StateR1 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & StateR1 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & StateR1 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & StateR1; -- Node name is '|crypter:2|~20~2' -- Equation name is '_LC090', type is buried -- synthesized logic cell _LC090 = LCELL( _EQ017 $ GND); _EQ017 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & StateR1 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & StateR1 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & StateR1 # _LC071 & StateR1 # StateR0 & StateR1; -- Node name is '|crypter:2|74162:37|:43' = '|crypter:2|74162:37|QA' -- Equation name is '_LC070', type is buried _LC070 = DFFE( _EQ018 $ _EQ019, _EQ020, VCC, VCC, VCC); _EQ018 = _X007; _X007 = EXP( _LC070 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ019 = !_LC116 & _X008; _X008 = EXP(!Encrypt0 & _LC070 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ020 = !_LC113 & !_LC114 & _X006; _X006 = EXP(!Clock & !StateR0 & StateR1 & StateR2 & !StateR3); -- Node name is '|crypter:2|74162:37|:44' = '|crypter:2|74162:37|QB' -- Equation name is '_LC068', type is buried _LC068 = DFFE( _EQ021 $ _EQ022, _EQ023, VCC, VCC, VCC); _EQ021 = _LC070 & !_LC071 & !_LC079 & !StateR0 & StateR1 & StateR2 & !StateR3 & _X009 & _X010 & _X011 & _X012; _X009 = EXP( Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068); _X010 = EXP( Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068); _X011 = EXP( Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068); _X012 = EXP( Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068); _EQ022 = _LC068 & !StateR0 & StateR1 & StateR2 & !StateR3; _EQ023 = !_LC113 & !_LC114 & _X006; _X006 = EXP(!Clock & !StateR0 & StateR1 & StateR2 & !StateR3); -- Node name is '|crypter:2|74162:37|:45' = '|crypter:2|74162:37|QC' -- Equation name is '_LC066', type is buried _LC066 = DFFE( _EQ024 $ _EQ025, _EQ026, VCC, VCC, VCC); _EQ024 = !Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC068 & _LC070 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 & _X013; _X013 = EXP( Encrypt0 & Encrypt1); _EQ025 = _LC066 & !StateR0 & StateR1 & StateR2 & !StateR3; _EQ026 = !_LC113 & !_LC114 & _X006; _X006 = EXP(!Clock & !StateR0 & StateR1 & StateR2 & !StateR3); -- Node name is '|crypter:2|74162:37|:46' = '|crypter:2|74162:37|QD' -- Equation name is '_LC079', type is buried _LC079 = DFFE( _EQ027 $ _EQ028, _EQ029, VCC, VCC, VCC); _EQ027 = _LC066 & _LC068 & _LC070 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 & _X014; _X014 = EXP( Encrypt0 & Encrypt1 & Encrypt2); _EQ028 = _LC079 & !_LC087 & !StateR0 & StateR1 & StateR2 & !StateR3; _EQ029 = !_LC113 & !_LC114 & _X006; _X006 = EXP(!Clock & !StateR0 & StateR1 & StateR2 & !StateR3); -- Node name is '|crypter:2|74162:37|~39~1' -- Equation name is '_LC116', type is buried -- synthesized logic cell _LC116 = LCELL( _EQ030 $ GND); _EQ030 = !Encrypt2 & _LC066 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt1 & !_LC068 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74162:37|~42~1' -- Equation name is '_LC087', type is buried -- synthesized logic cell _LC087 = LCELL( _EQ031 $ GND); _EQ031 = Encrypt1 & !_LC068 & _LC070 & !_LC071 # !Encrypt1 & _LC068 & _LC070 & !_LC071 # !Encrypt2 & _LC066 & _LC070 & !_LC071 # Encrypt2 & !_LC066 & _LC070 & !_LC071 # !Encrypt0 & _LC070 & !_LC071; -- Node name is '|crypter:2|74198:52|:113' = '|crypter:2|74198:52|QA' -- Equation name is '_LC122', type is buried _LC122 = DFFE( _EQ032 $ _EQ033, _EQ034, VCC, VCC, VCC); _EQ032 = !_LC126 & !_LC127 & !_LC128 & _X015; _X015 = EXP(!_LC111 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ033 = !_LC109 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ034 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|:114' = '|crypter:2|74198:52|QB' -- Equation name is '_LC111', type is buried _LC111 = DFFE( _EQ035 $ _EQ036, _EQ037, VCC, VCC, VCC); _EQ035 = !_LC100 & !_LC102 & !_LC125 & _X019; _X019 = EXP(!_LC101 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ036 = !_LC106 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ037 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|:115' = '|crypter:2|74198:52|QC' -- Equation name is '_LC101', type is buried _LC101 = DFFE( _EQ038 $ _EQ039, _EQ040, VCC, VCC, VCC); _EQ038 = !_LC098 & !_LC099 & !_LC112 & _X020; _X020 = EXP(!_LC082 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ039 = !_LC094 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ040 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|:116' = '|crypter:2|74198:52|QD' -- Equation name is '_LC082', type is buried _LC082 = DFFE( _EQ041 $ _EQ042, _EQ043, VCC, VCC, VCC); _EQ041 = !_LC083 & !_LC095 & !_LC096 & _X021; _X021 = EXP(!_LC081 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ042 = !_LC093 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ043 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|:117' = '|crypter:2|74198:52|QE' -- Equation name is '_LC081', type is buried _LC081 = DFFE( _EQ044 $ _EQ045, _EQ046, VCC, VCC, VCC); _EQ044 = !_LC084 & !_LC088 & !_LC118 & _X022; _X022 = EXP(!_LC081 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ045 = !_LC105 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ046 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|:118' = '|crypter:2|74198:52|QF' -- Equation name is '_LC108', type is buried _LC108 = DFFE( _EQ047 $ _EQ048, _EQ049, VCC, VCC, VCC); _EQ047 = !_LC103 & !_LC107 & !_LC110 & _X023; _X023 = EXP(!_LC092 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ048 = !_LC089 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ049 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|:119' = '|crypter:2|74198:52|QG' -- Equation name is '_LC092', type is buried _LC092 = DFFE( _EQ050 $ _EQ051, _EQ052, VCC, VCC, VCC); _EQ050 = !_LC085 & !_LC086 & !_LC104 & _X024; _X024 = EXP(!_LC092 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ051 = !_LC120 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ052 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|:120' = '|crypter:2|74198:52|QH' -- Equation name is '_LC121', type is buried _LC121 = DFFE( _EQ053 $ _EQ054, _EQ055, VCC, VCC, VCC); _EQ053 = !_LC119 & !_LC123 & !_LC124 & _X025; _X025 = EXP(!_LC121 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3); _EQ054 = !_LC073 & _X016; _X016 = EXP(!StateR0 & StateR1 & StateR2 & !StateR3); _EQ055 = !_LC090 & !_LC091 & StateR2 & !StateR3 & _X017 & _X018; _X017 = EXP(!Clock & StateR1); _X018 = EXP(!StateR0 & !StateR1); -- Node name is '|crypter:2|74198:52|~121~1' -- Equation name is '_LC128', type is buried -- synthesized logic cell _LC128 = LCELL( _EQ056 $ GND); _EQ056 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~121~2' -- Equation name is '_LC127', type is buried -- synthesized logic cell _LC127 = LCELL( _EQ057 $ GND); _EQ057 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~121~3' -- Equation name is '_LC126', type is buried -- synthesized logic cell _LC126 = LCELL( _EQ058 $ GND); _EQ058 = Encrypt1 & !_LC068 & !_LC071 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~122~1' -- Equation name is '_LC125', type is buried -- synthesized logic cell _LC125 = LCELL( _EQ059 $ GND); _EQ059 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~122~2' -- Equation name is '_LC102', type is buried -- synthesized logic cell _LC102 = LCELL( _EQ060 $ GND); _EQ060 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~122~3' -- Equation name is '_LC100', type is buried -- synthesized logic cell _LC100 = LCELL( _EQ061 $ GND); _EQ061 = Encrypt1 & !_LC068 & !_LC071 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC111 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~123~1' -- Equation name is '_LC099', type is buried -- synthesized logic cell _LC099 = LCELL( _EQ062 $ GND); _EQ062 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~123~2' -- Equation name is '_LC098', type is buried -- synthesized logic cell _LC098 = LCELL( _EQ063 $ GND); _EQ063 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~123~3' -- Equation name is '_LC112', type is buried -- synthesized logic cell _LC112 = LCELL( _EQ064 $ GND); _EQ064 = Encrypt1 & !_LC068 & !_LC071 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC101 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~124~1' -- Equation name is '_LC083', type is buried -- synthesized logic cell _LC083 = LCELL( _EQ065 $ GND); _EQ065 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~124~2' -- Equation name is '_LC096', type is buried -- synthesized logic cell _LC096 = LCELL( _EQ066 $ GND); _EQ066 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~124~3' -- Equation name is '_LC095', type is buried -- synthesized logic cell _LC095 = LCELL( _EQ067 $ GND); _EQ067 = Encrypt1 & !_LC068 & !_LC071 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC082 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~125~1' -- Equation name is '_LC118', type is buried -- synthesized logic cell _LC118 = LCELL( _EQ068 $ GND); _EQ068 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~125~2' -- Equation name is '_LC084', type is buried -- synthesized logic cell _LC084 = LCELL( _EQ069 $ GND); _EQ069 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~125~3' -- Equation name is '_LC088', type is buried -- synthesized logic cell _LC088 = LCELL( _EQ070 $ GND); _EQ070 = Encrypt1 & !_LC068 & !_LC071 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC081 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~126~1' -- Equation name is '_LC110', type is buried -- synthesized logic cell _LC110 = LCELL( _EQ071 $ GND); _EQ071 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~126~2' -- Equation name is '_LC103', type is buried -- synthesized logic cell _LC103 = LCELL( _EQ072 $ GND); _EQ072 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~126~3' -- Equation name is '_LC107', type is buried -- synthesized logic cell _LC107 = LCELL( _EQ073 $ GND); _EQ073 = Encrypt1 & !_LC068 & !_LC071 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC108 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~127~1' -- Equation name is '_LC104', type is buried -- synthesized logic cell _LC104 = LCELL( _EQ074 $ GND); _EQ074 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~127~2' -- Equation name is '_LC085', type is buried -- synthesized logic cell _LC085 = LCELL( _EQ075 $ GND); _EQ075 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~127~3' -- Equation name is '_LC086', type is buried -- synthesized logic cell _LC086 = LCELL( _EQ076 $ GND); _EQ076 = Encrypt1 & !_LC068 & !_LC071 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC092 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~128~1' -- Equation name is '_LC124', type is buried -- synthesized logic cell _LC124 = LCELL( _EQ077 $ GND); _EQ077 = Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & _LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & _LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & _LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & Encrypt1 & Encrypt2 & _LC066 & _LC068 & !_LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & _LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~128~2' -- Equation name is '_LC119', type is buried -- synthesized logic cell _LC119 = LCELL( _EQ078 $ GND); _EQ078 = !Encrypt0 & Encrypt1 & !Encrypt2 & !_LC066 & _LC068 & !_LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & Encrypt2 & _LC066 & !_LC068 & !_LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & !Encrypt1 & !Encrypt2 & !_LC066 & !_LC068 & !_LC070 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt2 & _LC066 & !_LC071 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt2 & !_LC066 & !_LC071 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|crypter:2|74198:52|~128~3' -- Equation name is '_LC123', type is buried -- synthesized logic cell _LC123 = LCELL( _EQ079 $ GND); _EQ079 = Encrypt1 & !_LC068 & !_LC071 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt1 & _LC068 & !_LC071 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # Encrypt0 & !_LC070 & !_LC071 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # !Encrypt0 & _LC070 & !_LC071 & !_LC122 & !StateR0 & StateR1 & StateR2 & !StateR3 # _LC071 & !_LC121 & !StateR0 & StateR1 & StateR2 & !StateR3; -- Node name is '|receivercntr:34|Q0~1' from file "receivercntr.tdf" line 9, column 24 -- Equation name is '_LC050', type is buried -- synthesized logic cell _LC050 = LCELL( _EQ080 $ GND); _EQ080 = !_LC054 & !_LC055 & !_LC057 & !StateR0 & !StateR1 & StateR2 & !StateR3 # !OutputAck & StateR0 & StateR1 & StateR2 & !StateR3 # !SendReq & !StateR0 & StateR1 & !StateR2 & !StateR3 # SendReq & !StateR0 & !StateR1 & !StateR2 & !StateR3 # !OutputAck & !StateR1 & !StateR2 & StateR3; -- Node name is '|74198:6|:113' = '|74198:6|QA' -- Equation name is '_LC109', type is buried _LC109 = DFFE( _LC106 $ GND, _EQ081, !Reset, VCC, VCC); _EQ081 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74198:6|:114' = '|74198:6|QB' -- Equation name is '_LC106', type is buried _LC106 = DFFE( _LC094 $ GND, _EQ082, !Reset, VCC, VCC); _EQ082 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74198:6|:115' = '|74198:6|QC' -- Equation name is '_LC094', type is buried _LC094 = DFFE( _LC093 $ GND, _EQ083, !Reset, VCC, VCC); _EQ083 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74198:6|:116' = '|74198:6|QD' -- Equation name is '_LC093', type is buried _LC093 = DFFE( _LC105 $ GND, _EQ084, !Reset, VCC, VCC); _EQ084 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74198:6|:117' = '|74198:6|QE' -- Equation name is '_LC105', type is buried _LC105 = DFFE( _LC089 $ GND, _EQ085, !Reset, VCC, VCC); _EQ085 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74198:6|:118' = '|74198:6|QF' -- Equation name is '_LC089', type is buried _LC089 = DFFE( _LC120 $ GND, _EQ086, !Reset, VCC, VCC); _EQ086 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74198:6|:119' = '|74198:6|QG' -- Equation name is '_LC120', type is buried _LC120 = DFFE( _LC073 $ GND, _EQ087, !Reset, VCC, VCC); _EQ087 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74198:6|:120' = '|74198:6|QH' -- Equation name is '_LC073', type is buried _LC073 = DFFE( Data $ GND, _EQ088, !Reset, VCC, VCC); _EQ088 = StateR0 & !StateR1 & !StateR2 & !StateR3; -- Node name is '|74393:7|:1' = '|74393:7|Q1A' -- Equation name is '_LC057', type is buried _LC057 = TFFE( VCC, _EQ089, !_EQ090, VCC, VCC); _EQ089 = _X026; _X026 = EXP( StateR0 & StateR1 & !StateR2 & !StateR3); _EQ090 = _X027; _X027 = EXP(!_LC052 & !Reset); -- Node name is '|74393:7|:3' = '|74393:7|Q1B' -- Equation name is '_LC055', type is buried _LC055 = TFFE( _LC057, _EQ091, !_EQ092, VCC, VCC); _EQ091 = _X026; _X026 = EXP( StateR0 & StateR1 & !StateR2 & !StateR3); _EQ092 = _X027; _X027 = EXP(!_LC052 & !Reset); -- Node name is '|74393:7|:5' = '|74393:7|Q1C' -- Equation name is '_LC054', type is buried _LC054 = TFFE( _EQ093, _EQ094, !_EQ095, VCC, VCC); _EQ093 = _LC055 & _LC057; _EQ094 = _X026; _X026 = EXP( StateR0 & StateR1 & !StateR2 & !StateR3); _EQ095 = _X027; _X027 = EXP(!_LC052 & !Reset); -- Node name is '|74393:7|:9' = '|74393:7|Q1D' -- Equation name is '_LC052', type is buried _LC052 = TFFE( _EQ096, _EQ097, !_EQ098, VCC, VCC); _EQ096 = _LC054 & _LC055 & _LC057; _EQ097 = _X026; _X026 = EXP( StateR0 & StateR1 & !StateR2 & !StateR3); _EQ098 = _X027; _X027 = EXP(!_LC052 & !Reset); -- Shareable expanders that are duplicated in multiple LABs: -- _X016 occurs in LABs F, G, H -- _X017 occurs in LABs F, G, H -- _X018 occurs in LABs F, G, H Project Information d:\lab6b\receiver.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Standard Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'MAX7000S' family DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on PARALLEL_EXPANDERS = off REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SOFT_BUFFER_INSERTION = on SUBFACTOR_EXTRACTION = on TURBO_BIT = on XOR_SYNTHESIS = on IGNORE_SOFT_BUFFERS = off USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off One-Hot State Machine Encoding = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = on Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:01 Logic Synthesizer 00:00:00 Partitioner 00:00:01 Fitter 00:00:00 Timing SNF Extractor 00:00:00 Assembler 00:00:02 -------------------------- -------- Total Time 00:00:04 Memory Allocated ----------------- Peak memory allocated during compilation = 6,178K