Project Information d:\s3g15\lab5\parallel\lab5.rpt MAX+plus II Compiler Report File Version 9.23 3/19/99 Compiled: 11/09/2000 15:40:54 Copyright (C) 1988-1999 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir Shareable POF Device Pins Pins Pins LCs Expanders % Utilized lab5 EPM7128SLC84-7 8 8 0 40 11 31 % User Pins: 8 8 0 Project Information d:\s3g15\lab5\parallel\lab5.rpt ** FILE HIERARCHY ** |modulefull:21| |modulefull:21|74183:6| |modulefull:25| |modulefull:25|74183:6| |modulefull:24| |modulefull:24|74183:6| |modulefull:23| |modulefull:23|74183:6| |modulefull:22| |modulefull:22|74183:6| |modulefull:20| |modulefull:20|74183:6| |modulefull:19| |modulefull:19|74183:6| |modulefull:18| |modulefull:18|74183:6| |modulefull:17| |modulefull:17|74183:6| |modulefull:15| |modulefull:15|74183:6| |modulefull:13| |modulefull:13|74183:6| |modulefull:11| |modulefull:11|74183:6| Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ***** Logic for device 'lab5' compiled without errors. Device: EPM7128SLC84-7 Device Options: Turbo Bit = ON Security Bit = OFF Enable JTAG Support = ON User Code = ffff MultiVolt I/O = OFF R R R R R E E E E E V S S S S S C E E E V E E C R R R C R R G I G G G G G V V V C V V x x x y N y y y N N N N N N E E E I E p E 1 2 3 0 D 1 2 3 T D D D D D D D D O D 7 D -----------------------------------------------------------------_ / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | x0 | 12 74 | p6 VCCIO | 13 73 | p5 #TDI | 14 72 | GND RESERVED | 15 71 | #TDO RESERVED | 16 70 | RESERVED RESERVED | 17 69 | RESERVED RESERVED | 18 68 | RESERVED GND | 19 67 | p4 RESERVED | 20 66 | VCCIO RESERVED | 21 65 | p3 RESERVED | 22 EPM7128SLC84-7 64 | p1 #TMS | 23 63 | p0 RESERVED | 24 62 | #TCK RESERVED | 25 61 | RESERVED VCCIO | 26 60 | RESERVED RESERVED | 27 59 | GND RESERVED | 28 58 | RESERVED RESERVED | 29 57 | RESERVED RESERVED | 30 56 | RESERVED RESERVED | 31 55 | RESERVED GND | 32 54 | p2 |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _| ------------------------------------------------------------------ R R R R R V R R R G V R R R G R R R R R V E E E E E C E E E N C E E E N E E E E E C S S S S S C S S S D C S S S D S S S S S C E E E E E I E E E I E E E E E E E E I R R R R R O R R R N R R R R R R R R O V V V V V V V V T V V V V V V V V E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D N.C. = No Connect, This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** RESOURCE USAGE ** Shareable External Logic Array Block Logic Cells I/O Pins Expanders Interconnect A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%) B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) D: LC49 - LC64 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%) E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%) F: LC81 - LC96 8/16( 50%) 2/ 8( 25%) 9/16( 56%) 18/36( 50%) G: LC97 - LC112 16/16(100%) 5/ 8( 62%) 11/16( 68%) 13/36( 36%) H: LC113 - LC128 16/16(100%) 3/ 8( 37%) 16/16(100%) 24/36( 66%) Total dedicated input pins used: 0/4 ( 0%) Total I/O pins used: 20/64 ( 31%) Total logic cells used: 40/128 ( 31%) Total shareable expanders used: 11/128 ( 8%) Total Turbo logic cells used: 40/128 ( 31%) Total shareable expanders not available (n/a): 25/128 ( 19%) Average fan-in: 7.10 Total fan-in: 284 Total input pins required: 8 Total fast input logic cells required: 0 Total output pins required: 8 Total bidirectional pins required: 0 Total reserved pins required 4 Total logic cells required: 40 Total flipflops required: 0 Total product terms required: 175 Total logic cells lending parallel expanders: 0 Total shareable expanders in database: 11 Synthesized logic cells: 32/ 128 ( 25%) Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** INPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 12 (3) (A) INPUT 0 0 0 0 0 6 19 x0 11 (5) (A) INPUT 0 0 0 0 0 4 21 x1 10 (6) (A) INPUT 0 0 0 0 0 2 29 x2 9 (8) (A) INPUT 0 0 0 0 0 2 27 x3 8 (11) (A) INPUT 0 0 0 0 0 4 22 y0 6 (13) (A) INPUT 0 0 0 0 0 3 22 y1 5 (14) (A) INPUT 0 0 0 0 0 2 26 y2 4 (16) (A) INPUT 0 0 0 0 0 4 13 y3 Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** OUTPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 63 97 G OUTPUT t 0 0 0 2 0 0 0 p0 64 99 G OUTPUT t 1 0 1 4 0 0 0 p1 54 83 F OUTPUT t 2 0 1 6 1 0 0 p2 65 101 G OUTPUT t 1 0 0 2 4 0 0 p3 67 104 G OUTPUT t 1 0 0 3 5 0 0 p4 73 115 H OUTPUT t 0 0 0 0 6 0 0 p5 74 117 H OUTPUT t 0 0 0 2 2 0 0 p6 76 120 H OUTPUT t 1 0 1 8 4 0 0 p7 Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** BURIED LOGIC ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name - 110 G SOFT s t 0 0 0 6 0 0 9 |modulefull:17|74183:6|~8~1 - 102 G SOFT s t 1 0 1 6 0 1 0 |modulefull:18|74183:6|1SUM~1 (|modulefull:18|74183:6|~7~1) - 84 F SOFT s t 0 0 0 7 0 2 1 |modulefull:19|74183:6|~9~1 - 82 F SOFT s t 1 0 1 7 1 2 1 |modulefull:19|74183:6|~10~1 - 100 G SOFT s t 1 0 1 6 0 0 1 |modulefull:19|74183:6|~10~2 (77) 123 H SOFT s t 0 0 0 7 0 2 1 |modulefull:19|74183:6|~11~1 - 98 G SOFT s t 0 0 0 7 0 2 1 |modulefull:19|74183:6|~12~1 (58) 91 F SOFT s t 1 0 1 7 3 1 1 |modulefull:20|74183:6|~7~1 (70) 109 G SOFT s t 1 0 1 7 0 0 1 |modulefull:20|74183:6|1SUM~2 (|modulefull:20|74183:6|~7~2) - 108 G SOFT s t 1 0 1 6 0 0 1 |modulefull:20|74183:6|1SUM~3 (|modulefull:20|74183:6|~7~3) (69) 107 G SOFT s t 0 0 0 6 0 0 1 |modulefull:20|74183:6|1SUM~4 (|modulefull:20|74183:6|~7~4) - 90 F SOFT s t 3 0 1 7 1 2 4 |modulefull:20|74183:6|~8~1 (68) 105 G SOFT s t 1 0 1 6 0 0 1 |modulefull:20|74183:6|1CN1~2 (|modulefull:20|74183:6|~8~2) (57) 88 F SOFT s t 0 0 0 2 0 0 3 |modulefull:21|~5~1 - 106 G SOFT s t 1 0 1 7 0 2 0 |modulefull:21|74183:6|~8~1 - 111 G SOFT s t 1 0 1 7 0 0 1 |modulefull:21|74183:6|1CN1~2 (|modulefull:21|74183:6|~8~2) - 92 F SOFT s t 2 0 1 7 1 1 0 |modulefull:21|74183:6|~13~1 - 103 G SOFT s t 0 0 0 2 5 0 7 |modulefull:23|74183:6|~13~1 (79) 125 H SOFT s t 4 1 1 8 2 0 8 |modulefull:23|74183:6|~14~1 - 124 H SOFT s t 1 0 1 8 0 0 1 |modulefull:23|74183:6|~14~2 (71) 112 G SOFT s t 1 0 1 7 0 0 1 |modulefull:23|74183:6|~14~3 - 119 H SOFT s t 4 1 1 8 0 0 8 |modulefull:23|74183:6|~15~1 (81) 128 H SOFT s t 1 0 1 2 5 1 0 |modulefull:24|74183:6|1SUM~1 (|modulefull:24|74183:6|~7~1) - 127 H SOFT s t 1 0 1 2 5 1 0 |modulefull:24|74183:6|1SUM~2 (|modulefull:24|74183:6|~7~2) (80) 126 H SOFT s t 1 0 1 4 5 1 0 |modulefull:24|74183:6|1SUM~3 (|modulefull:24|74183:6|~7~3) - 122 H SOFT s t 1 0 1 4 4 1 0 |modulefull:24|74183:6|1SUM~4 (|modulefull:24|74183:6|~7~4) - 121 H SOFT s t 0 0 0 4 3 1 0 |modulefull:24|74183:6|1SUM~5 (|modulefull:24|74183:6|~7~5) - 81 F SOFT s t 0 0 0 0 4 2 0 |modulefull:24|74183:6|~8~1 - 113 H SOFT s t 1 0 1 7 5 0 1 |modulefull:24|74183:6|1CN1~2 (|modulefull:24|74183:6|~8~2) - 114 H SOFT s t 1 0 1 6 5 0 1 |modulefull:24|74183:6|1CN1~3 (|modulefull:24|74183:6|~8~3) - 116 H SOFT s t 1 0 1 5 5 0 1 |modulefull:24|74183:6|1CN1~4 (|modulefull:24|74183:6|~8~4) (75) 118 H SOFT s t 0 0 0 4 2 0 1 |modulefull:24|74183:6|1CN1~5 (|modulefull:24|74183:6|~8~5) Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'F': Logic cells placed in LAB 'F' +--------------- LC84 |modulefull:19|74183:6|~9~1 | +------------- LC82 |modulefull:19|74183:6|~10~1 | | +----------- LC91 |modulefull:20|74183:6|~7~1 | | | +--------- LC90 |modulefull:20|74183:6|~8~1 | | | | +------- LC88 |modulefull:21|~5~1 | | | | | +----- LC92 |modulefull:21|74183:6|~13~1 | | | | | | +--- LC81 |modulefull:24|74183:6|~8~1 | | | | | | | +- LC83 p2 | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | that feed LAB 'F' LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F': Pin 12 -> * * * * - * - * | - - - - - * * * | <-- x0 11 -> * * * * - * - * | - - - - - * * * | <-- x1 10 -> * * * * - * - * | - - - - - * * * | <-- x2 9 -> * * * * * * - - | - - - - - * * * | <-- x3 8 -> * * * * - * - * | - - - - - * * * | <-- y0 6 -> * * * * - * - * | - - - - - * * * | <-- y1 5 -> * * * * * * - * | - - - - - * * * | <-- y2 LC102-> - - - - - - - * | - - - - - * - - | <-- |modulefull:18|74183:6|1SUM~1 LC100-> - * - - - - - - | - - - - - * - - | <-- |modulefull:19|74183:6|~10~2 LC109-> - - * - - - - - | - - - - - * - - | <-- |modulefull:20|74183:6|1SUM~2 LC108-> - - * - - - - - | - - - - - * - - | <-- |modulefull:20|74183:6|1SUM~3 LC107-> - - * - - - - - | - - - - - * - - | <-- |modulefull:20|74183:6|1SUM~4 LC105-> - - - * - - - - | - - - - - * - - | <-- |modulefull:20|74183:6|1CN1~2 LC111-> - - - - - * - - | - - - - - * - - | <-- |modulefull:21|74183:6|1CN1~2 LC113-> - - - - - - * - | - - - - - * - - | <-- |modulefull:24|74183:6|1CN1~2 LC114-> - - - - - - * - | - - - - - * - - | <-- |modulefull:24|74183:6|1CN1~3 LC116-> - - - - - - * - | - - - - - * - - | <-- |modulefull:24|74183:6|1CN1~4 LC118-> - - - - - - * - | - - - - - * - - | <-- |modulefull:24|74183:6|1CN1~5 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'G': Logic cells placed in LAB 'G' +------------------------------- LC110 |modulefull:17|74183:6|~8~1 | +----------------------------- LC102 |modulefull:18|74183:6|1SUM~1 | | +--------------------------- LC100 |modulefull:19|74183:6|~10~2 | | | +------------------------- LC98 |modulefull:19|74183:6|~12~1 | | | | +----------------------- LC109 |modulefull:20|74183:6|1SUM~2 | | | | | +--------------------- LC108 |modulefull:20|74183:6|1SUM~3 | | | | | | +------------------- LC107 |modulefull:20|74183:6|1SUM~4 | | | | | | | +----------------- LC105 |modulefull:20|74183:6|1CN1~2 | | | | | | | | +--------------- LC106 |modulefull:21|74183:6|~8~1 | | | | | | | | | +------------- LC111 |modulefull:21|74183:6|1CN1~2 | | | | | | | | | | +----------- LC103 |modulefull:23|74183:6|~13~1 | | | | | | | | | | | +--------- LC112 |modulefull:23|74183:6|~14~3 | | | | | | | | | | | | +------- LC97 p0 | | | | | | | | | | | | | +----- LC99 p1 | | | | | | | | | | | | | | +--- LC101 p3 | | | | | | | | | | | | | | | +- LC104 p4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'G' LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G': LC98 -> - - - - - - - - - - * - - - * * | - - - - - - * - | <-- |modulefull:19|74183:6|~12~1 Pin 12 -> * * - * * - - * * * * * * * * * | - - - - - * * * | <-- x0 11 -> * * * * * * * * * * - * - * - * | - - - - - * * * | <-- x1 10 -> * * * * * * * * * * - * - - - - | - - - - - * * * | <-- x2 9 -> * - * * * * * * * * - * - - - - | - - - - - * * * | <-- x3 8 -> * * * * * * * * * * - * * * - - | - - - - - * * * | <-- y0 6 -> * * * * * * * * * * - * - * - - | - - - - - * * * | <-- y1 5 -> - * * * * * * - * * - * - - - - | - - - - - * * * | <-- y2 4 -> - - - - - - - - - - * - - - * * | - - - - - - * * | <-- y3 LC84 -> - - - - - - - - - - * - - - * * | - - - - - - * - | <-- |modulefull:19|74183:6|~9~1 LC82 -> - - - - - - - - - - * - - - * * | - - - - - - * - | <-- |modulefull:19|74183:6|~10~1 LC123-> - - - - - - - - - - * - - - * * | - - - - - - * - | <-- |modulefull:19|74183:6|~11~1 LC91 -> - - - - - - - - - - * - - - - * | - - - - - - * - | <-- |modulefull:20|74183:6|~7~1 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'H': Logic cells placed in LAB 'H' +------------------------------- LC123 |modulefull:19|74183:6|~11~1 | +----------------------------- LC125 |modulefull:23|74183:6|~14~1 | | +--------------------------- LC124 |modulefull:23|74183:6|~14~2 | | | +------------------------- LC119 |modulefull:23|74183:6|~15~1 | | | | +----------------------- LC128 |modulefull:24|74183:6|1SUM~1 | | | | | +--------------------- LC127 |modulefull:24|74183:6|1SUM~2 | | | | | | +------------------- LC126 |modulefull:24|74183:6|1SUM~3 | | | | | | | +----------------- LC122 |modulefull:24|74183:6|1SUM~4 | | | | | | | | +--------------- LC121 |modulefull:24|74183:6|1SUM~5 | | | | | | | | | +------------- LC113 |modulefull:24|74183:6|1CN1~2 | | | | | | | | | | +----------- LC114 |modulefull:24|74183:6|1CN1~3 | | | | | | | | | | | +--------- LC116 |modulefull:24|74183:6|1CN1~4 | | | | | | | | | | | | +------- LC118 |modulefull:24|74183:6|1CN1~5 | | | | | | | | | | | | | +----- LC115 p5 | | | | | | | | | | | | | | +--- LC117 p6 | | | | | | | | | | | | | | | +- LC120 p7 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'H' LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H': LC125-> - - - - * * * * * * * * - - - - | - - - - - - - * | <-- |modulefull:23|74183:6|~14~1 LC124-> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- |modulefull:23|74183:6|~14~2 LC119-> - - - - * * * * * * * * - - - - | - - - - - - - * | <-- |modulefull:23|74183:6|~15~1 LC128-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |modulefull:24|74183:6|1SUM~1 LC127-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |modulefull:24|74183:6|1SUM~2 LC126-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |modulefull:24|74183:6|1SUM~3 LC122-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |modulefull:24|74183:6|1SUM~4 LC121-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |modulefull:24|74183:6|1SUM~5 Pin 12 -> * * * * - - - - - * - - - - - * | - - - - - * * * | <-- x0 11 -> * * * * - - - - - - - * - - - * | - - - - - * * * | <-- x1 10 -> * * * * * * * * * * * * * - - * | - - - - - * * * | <-- x2 9 -> * * * * - - * * * * * * * - * * | - - - - - * * * | <-- x3 8 -> * * * * - - - - - * * - - - - * | - - - - - * * * | <-- y0 6 -> * * * * - - - - - * * - - - - * | - - - - - * * * | <-- y1 5 -> * * * * - - * * * * * * * - - * | - - - - - * * * | <-- y2 4 -> - * * * * * * * * * * * * - * * | - - - - - - * * | <-- y3 LC110-> - - - - * * * * * * * * * - - - | - - - - - - - * | <-- |modulefull:17|74183:6|~8~1 LC90 -> - - - - - - - - - * * * * * - * | - - - - - - - * | <-- |modulefull:20|74183:6|~8~1 LC88 -> - - - - * * * - - - - - - - - - | - - - - - - - * | <-- |modulefull:21|~5~1 LC106-> - - - - - - - - - - - - - - * * | - - - - - - - * | <-- |modulefull:21|74183:6|~8~1 LC92 -> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- |modulefull:21|74183:6|~13~1 LC103-> - - - - * * * * - * * * - - - - | - - - - - - - * | <-- |modulefull:23|74183:6|~13~1 LC112-> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- |modulefull:23|74183:6|~14~3 LC81 -> - - - - - - - - - - - - - - * * | - - - - - - - * | <-- |modulefull:24|74183:6|~8~1 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\s3g15\lab5\parallel\lab5.rpt lab5 ** EQUATIONS ** x0 : INPUT; x1 : INPUT; x2 : INPUT; x3 : INPUT; y0 : INPUT; y1 : INPUT; y2 : INPUT; y3 : INPUT; -- Node name is 'p0' -- Equation name is 'p0', location is LC097, type is output. p0 = LCELL( _EQ001 $ GND); _EQ001 = x0 & y0; -- Node name is 'p1' -- Equation name is 'p1', location is LC099, type is output. p1 = LCELL( _EQ002 $ x0); _EQ002 = x0 & x1 & y0 & y1 # !x0 & x1 & y0 # x0 & !x1 & !y1 # x0 & !y0 & !y1; -- Node name is 'p2' -- Equation name is 'p2', location is LC083, type is output. p2 = LCELL( _EQ003 $ _EQ004); _EQ003 = !_LC102 & !x0 & x1 & _X001 & x2 & y0 & y1 # !_LC102 & x0 & x1 & _X001 & !y0 & y1 & y2 # !_LC102 & x0 & _X001 & x2 & y0 & y2 # !_LC102 & x0 & _X001 & !x2 & y0 & !y2; _X001 = EXP(!x0 & !x2 & !y1); _EQ004 = !_LC102 & _X001; _X001 = EXP(!x0 & !x2 & !y1); -- Node name is 'p3' -- Equation name is 'p3', location is LC101, type is output. p3 = LCELL( _EQ005 $ VCC); _EQ005 = !_LC082 & !_LC084 & !_LC098 & !_LC123 & x0 & y3 # _X002 & !y3 # !x0 & _X002; _X002 = EXP(!_LC082 & !_LC084 & !_LC098 & !_LC123); -- Node name is 'p4' -- Equation name is 'p4', location is LC104, type is output. p4 = LCELL( _EQ006 $ _LC091); _EQ006 = !_LC082 & !_LC084 & !_LC098 & !_LC123 & x0 & !x1 & y3 # x1 & _X003 & y3; _X003 = EXP(!_LC082 & !_LC084 & !_LC098 & !_LC123 & x0); -- Node name is 'p5' -- Equation name is 'p5', location is LC115, type is output. p5 = LCELL( _EQ007 $ !_LC090); _EQ007 = !_LC121 & !_LC122 & !_LC126 & !_LC127 & !_LC128; -- Node name is 'p6' -- Equation name is 'p6', location is LC117, type is output. p6 = LCELL( _EQ008 $ _LC081); _EQ008 = !_LC106 & x3 & y3 # _LC106 & !y3 # _LC106 & !x3; -- Node name is 'p7' -- Equation name is 'p7', location is LC120, type is output. p7 = LCELL( _EQ009 $ GND); _EQ009 = _LC081 & _LC090 & !_LC092 & x0 & x1 & x3 & y0 & y1 # _LC081 & _LC090 & !_LC092 & x2 & x3 & y0 & y1 # _LC081 & !_LC092 & x3 & y2 # _LC081 & x3 & y3 # _LC106 & x3 & y3; -- Node name is '|modulefull:17|74183:6|~8~1' -- Equation name is '_LC110', type is buried -- synthesized logic cell _LC110 = LCELL( _EQ010 $ GND); _EQ010 = x0 & x1 & x3 & y0 & y1 # x2 & x3 & y0 & y1; -- Node name is '|modulefull:18|74183:6|~7~1' = '|modulefull:18|74183:6|1SUM~1' -- Equation name is '_LC102', type is buried -- synthesized logic cell _LC102 = LCELL( _EQ011 $ GND); _EQ011 = !x1 & !y0 & !y2 # !y0 & !y1 & !y2 # !x0 & !x1 & !x2 # !x0 & !x1 & !y0 # !x0 & !y0 & !y1; -- Node name is '|modulefull:19|74183:6|~9~1' -- Equation name is '_LC084', type is buried -- synthesized logic cell _LC084 = LCELL( _EQ012 $ GND); _EQ012 = x0 & x1 & x2 & !x3 & y0 & y2 # x0 & x1 & !x2 & !y0 & y1 & y2; -- Node name is '|modulefull:19|74183:6|~10~1' -- Equation name is '_LC082', type is buried -- synthesized logic cell _LC082 = LCELL( _EQ013 $ !_LC100); _EQ013 = !_LC100 & x0 & x1 & !x2 & !x3 & y0 & y1 # !_LC100 & x0 & x2 & y0 & y2 # !_LC100 & x1 & x2 & x3 & y1 # !_LC100 & !x0 & x1 & x3 & y0; -- Node name is '|modulefull:19|74183:6|~10~2' -- Equation name is '_LC100', type is buried -- synthesized logic cell _LC100 = LCELL( _EQ014 $ GND); _EQ014 = !x1 & x2 & !x3 & y1 # !x1 & !x2 & x3 & y0 # x2 & !y0 & y1 # x3 & y0 & !y1 # x1 & y2; -- Node name is '|modulefull:19|74183:6|~11~1' -- Equation name is '_LC123', type is buried -- synthesized logic cell _LC123 = LCELL( _EQ015 $ GND); _EQ015 = x0 & x1 & !x2 & !x3 & y0 & y1 & y2 # !x0 & x1 & x2 & !y0 & y1 & y2 # x1 & !x2 & x3 & y0 & !y1 & y2 # !x0 & x1 & x3 & y0 & y2; -- Node name is '|modulefull:19|74183:6|~12~1' -- Equation name is '_LC098', type is buried -- synthesized logic cell _LC098 = LCELL( _EQ016 $ GND); _EQ016 = x0 & !x1 & x2 & !x3 & y0 & y1 & y2 # x0 & !x1 & x2 & x3 & y0 & !y1 & y2; -- Node name is '|modulefull:20|74183:6|~8~2' = '|modulefull:20|74183:6|1CN1~2' -- Equation name is '_LC105', type is buried -- synthesized logic cell _LC105 = LCELL( _EQ017 $ GND); _EQ017 = !x0 & !x2 & !y0 # !x0 & !x3 & !y1 # !x1 & !x3 & !y0 # !y0 & !y1 # !x2 & !y1; -- Node name is '|modulefull:20|74183:6|~7~2' = '|modulefull:20|74183:6|1SUM~2' -- Equation name is '_LC109', type is buried -- synthesized logic cell _LC109 = LCELL( _EQ018 $ GND); _EQ018 = x0 & x2 & x3 & y0 & !y1 # x0 & x1 & x2 & y0 & !y1 # !x0 & x1 & !x3 & y1 & y2 # x0 & !x1 & !x3 & y0 & y1 # x1 & x2 & !x3 & !y0 & y1; -- Node name is '|modulefull:20|74183:6|~7~3' = '|modulefull:20|74183:6|1SUM~3' -- Equation name is '_LC108', type is buried -- synthesized logic cell _LC108 = LCELL( _EQ019 $ GND); _EQ019 = x1 & x2 & x3 & y0 # !x1 & x2 & y0 & !y2 # !x2 & !y0 & !y1 # !x1 & !x2 & !y1 # !x2 & !x3 & !y1; -- Node name is '|modulefull:20|74183:6|~7~4' = '|modulefull:20|74183:6|1SUM~4' -- Equation name is '_LC107', type is buried -- synthesized logic cell _LC107 = LCELL( _EQ020 $ GND); _EQ020 = !x3 & !y0 & !y2 # !x2 & !x3 & !y2 # !x1 & !x2 & !x3 # !y1 & !y2; -- Node name is '|modulefull:20|74183:6|~7~1' -- Equation name is '_LC091', type is buried -- synthesized logic cell _LC091 = LCELL( _EQ021 $ _EQ022); _EQ021 = !_LC107 & !_LC108 & !_LC109 & x0 & x1 & !x2 & x3 & y1 & y2 # !_LC107 & !_LC108 & !_LC109 & !x1 & x2 & x3 & !y0 & y1 & y2 # !_LC107 & !_LC108 & !_LC109 & x1 & x3 & y0 & y1 & y2 # !_LC107 & !_LC108 & !_LC109 & x0 & x1 & x3 & y0 & y1; _EQ022 = !_LC107 & !_LC108 & !_LC109; -- Node name is '|modulefull:20|74183:6|~8~1' -- Equation name is '_LC090', type is buried -- synthesized logic cell _LC090 = LCELL( _EQ023 $ _EQ024); _EQ023 = !_LC105 & !x1 & x3 & _X004 & _X005 & y0 & y1 & y2 # !_LC105 & x0 & !x2 & _X004 & _X005 & y0 & y2 # !_LC105 & !x0 & !x1 & _X004 & _X005 & y0 & y2 # !_LC105 & !x1 & !x3 & _X004 & _X005 & !y1 & y2; _X004 = EXP(!x1 & !x2); _X005 = EXP(!x2 & !x3); _EQ024 = !_LC105 & _X004 & _X005 & y2; _X004 = EXP(!x1 & !x2); _X005 = EXP(!x2 & !x3); -- Node name is '|modulefull:21|~5~1' -- Equation name is '_LC088', type is buried -- synthesized logic cell _LC088 = LCELL( _EQ025 $ GND); _EQ025 = x3 & y2; -- Node name is '|modulefull:21|74183:6|~8~2' = '|modulefull:21|74183:6|1CN1~2' -- Equation name is '_LC111', type is buried -- synthesized logic cell _LC111 = LCELL( _EQ026 $ GND); _EQ026 = x0 & x2 & x3 & y0 & y2 # x2 & x3 & y1 & y2 # x0 & x1 & x3 & y0 & y1 # x0 & x2 & y0 & y1 & y2 # x1 & x2 & y1 & y2; -- Node name is '|modulefull:21|74183:6|~8~1' -- Equation name is '_LC106', type is buried -- synthesized logic cell _LC106 = LCELL( _EQ027 $ GND); _EQ027 = x1 & x2 & x3 & y0 & y2 # x0 & x2 & x3 & y0 & y2 # x1 & x3 & y0 & y1 & y2 # x0 & x1 & x3 & y1 & y2 # x2 & x3 & y1 & y2; -- Node name is '|modulefull:21|74183:6|~13~1' -- Equation name is '_LC092', type is buried -- synthesized logic cell _LC092 = LCELL( _EQ028 $ _EQ029); _EQ028 = !_LC111 & x1 & x3 & _X006 & y0 & y1 & y2 # !_LC111 & x0 & x1 & x3 & _X006 & y1 & y2 # !_LC111 & x1 & x2 & x3 & _X006 & y0 & y2 # !_LC111 & x0 & x1 & x2 & _X006 & y0 & y2; _X006 = EXP( x2 & x3 & y0 & y1); _EQ029 = !_LC111 & _X006; _X006 = EXP( x2 & x3 & y0 & y1); -- Node name is '|modulefull:23|74183:6|~13~1' -- Equation name is '_LC103', type is buried -- synthesized logic cell _LC103 = LCELL( _EQ030 $ !_LC091); _EQ030 = !_LC082 & !_LC084 & !_LC091 & !_LC098 & !_LC123 & x0 & y3; -- Node name is '|modulefull:23|74183:6|~14~1' -- Equation name is '_LC125', type is buried -- synthesized logic cell _LC125 = LCELL( _EQ031 $ _EQ032); _EQ031 = !_LC112 & !_LC124 & x0 & x1 & x2 & !x3 & _X007 & _X008 & _X009 & y0 & y1 # !_LC112 & !_LC124 & x0 & x1 & !x2 & !x3 & _X007 & _X008 & _X009 & y1 & y2 # !_LC112 & !_LC124 & x1 & !x2 & x3 & _X007 & _X008 & _X009 & y0 & !y1 & y2 # !_LC112 & !_LC124 & x1 & x2 & !x3 & _X007 & _X008 & _X009 & y0 & y1 & !y2; _X007 = EXP( x1 & y3); _X008 = EXP(!x1 & !x2 & x3 & y1); _X009 = EXP( x3 & !y0 & y1 & !y2); _EQ032 = !_LC112 & !_LC124 & _X007 & _X008 & _X009; _X007 = EXP( x1 & y3); _X008 = EXP(!x1 & !x2 & x3 & y1); _X009 = EXP( x3 & !y0 & y1 & !y2); -- Node name is '|modulefull:23|74183:6|~14~2' -- Equation name is '_LC124', type is buried -- synthesized logic cell _LC124 = LCELL( _EQ033 $ GND); _EQ033 = !x1 & x3 & y0 & y1 & y2 # x1 & x2 & x3 & !y0 & y2 # !x0 & !x1 & x2 & y0 & y2 # !x0 & x1 & x3 & !y0 & y1 # !x0 & x2 & !x3 & y2 & y3; -- Node name is '|modulefull:23|74183:6|~14~3' -- Equation name is '_LC112', type is buried -- synthesized logic cell _LC112 = LCELL( _EQ034 $ GND); _EQ034 = !x1 & x2 & !x3 & !y1 & y2 # !x0 & x2 & !x3 & !y1 & y2 # !x1 & x2 & !x3 & !y0 & y2 # !x0 & !x2 & x3 & y1 & !y2 # x2 & !y0 & !y1 & y2; -- Node name is '|modulefull:23|74183:6|~15~1' -- Equation name is '_LC119', type is buried -- synthesized logic cell _LC119 = LCELL( _EQ035 $ _EQ036); _EQ035 = x0 & x2 & !x3 & _X007 & _X010 & _X011 & y0 & !y1 & y2 & y3 # x0 & x3 & _X007 & _X010 & _X011 & y0 & y1 & y2 & y3 # x0 & x2 & !x3 & _X007 & _X010 & _X011 & y1 & !y2 & y3 # x0 & x3 & _X007 & _X010 & _X011 & y0 & !y1 & !y2 & y3; _X007 = EXP( x1 & y3); _X010 = EXP( x0 & !x2 & x3 & y0 & y3); _X011 = EXP( x0 & x2 & !y0 & y1 & y3); _EQ036 = _X007 & _X010 & _X011; _X007 = EXP( x1 & y3); _X010 = EXP( x0 & !x2 & x3 & y0 & y3); _X011 = EXP( x0 & x2 & !y0 & y1 & y3); -- Node name is '|modulefull:24|74183:6|~8~2' = '|modulefull:24|74183:6|1CN1~2' -- Equation name is '_LC113', type is buried -- synthesized logic cell _LC113 = LCELL( _EQ037 $ GND); _EQ037 = !_LC103 & !_LC119 & x2 & x3 & y0 & y1 & y2 & y3 # !_LC103 & !_LC119 & x2 & x3 & !y0 & y1 & !y2 & y3 # !_LC103 & !_LC119 & !x0 & x2 & y0 & y2 & y3 # _LC090 & !_LC103 & _LC110 & !_LC119 & !_LC125 & x3 & y2 # !_LC103 & !_LC119 & x2 & !x3 & !y0 & y2 & y3; -- Node name is '|modulefull:24|74183:6|~8~3' = '|modulefull:24|74183:6|1CN1~3' -- Equation name is '_LC114', type is buried -- synthesized logic cell _LC114 = LCELL( _EQ038 $ GND); _EQ038 = !_LC103 & !_LC119 & x2 & !x3 & !y1 & y2 & y3 # !_LC103 & !_LC119 & x2 & !y0 & !y1 & y2 & y3 # !_LC090 & !_LC103 & !_LC110 & !_LC119 & !_LC125 & x3 & y2 # _LC090 & _LC110 & x2 & x3 & y2 & y3 # !_LC090 & !_LC110 & x2 & x3 & y2 & y3; -- Node name is '|modulefull:24|74183:6|~8~4' = '|modulefull:24|74183:6|1CN1~4' -- Equation name is '_LC116', type is buried -- synthesized logic cell _LC116 = LCELL( _EQ039 $ GND); _EQ039 = _LC090 & !_LC103 & !_LC110 & !_LC119 & !_LC125 & !y2 # _LC090 & !_LC103 & !_LC110 & !_LC119 & !_LC125 & !x3 # !_LC090 & !_LC103 & _LC110 & !_LC119 & !_LC125 & !y2 # !_LC090 & !_LC103 & _LC110 & !_LC119 & !_LC125 & !x3 # !_LC103 & !_LC119 & x1 & x2 & y3; -- Node name is '|modulefull:24|74183:6|~8~5' = '|modulefull:24|74183:6|1CN1~5' -- Equation name is '_LC118', type is buried -- synthesized logic cell _LC118 = LCELL( _EQ040 $ GND); _EQ040 = _LC090 & !_LC110 & x2 & !y2 & y3 # _LC090 & !_LC110 & x2 & !x3 & y3 # !_LC090 & _LC110 & x2 & !y2 & y3 # !_LC090 & _LC110 & x2 & !x3 & y3; -- Node name is '|modulefull:24|74183:6|~7~1' = '|modulefull:24|74183:6|1SUM~1' -- Equation name is '_LC128', type is buried -- synthesized logic cell _LC128 = LCELL( _EQ041 $ GND); _EQ041 = !_LC088 & !_LC103 & _LC110 & !_LC119 & !_LC125 & x2 & y3 # !_LC088 & !_LC103 & !_LC110 & !_LC119 & !_LC125 & !y3 # !_LC088 & !_LC103 & !_LC110 & !_LC119 & !_LC125 & !x2 # !_LC088 & _LC103 & !_LC110 & x2 & y3 # !_LC088 & !_LC110 & _LC125 & x2 & y3; -- Node name is '|modulefull:24|74183:6|~7~2' = '|modulefull:24|74183:6|1SUM~2' -- Equation name is '_LC127', type is buried -- synthesized logic cell _LC127 = LCELL( _EQ042 $ GND); _EQ042 = !_LC088 & !_LC110 & _LC119 & x2 & y3 # !_LC088 & _LC103 & _LC110 & !y3 # !_LC088 & _LC103 & _LC110 & !x2 # !_LC088 & _LC110 & _LC125 & !y3 # !_LC088 & _LC110 & _LC125 & !x2; -- Node name is '|modulefull:24|74183:6|~7~3' = '|modulefull:24|74183:6|1SUM~3' -- Equation name is '_LC126', type is buried -- synthesized logic cell _LC126 = LCELL( _EQ043 $ GND); _EQ043 = !_LC088 & _LC110 & _LC119 & !y3 # !_LC088 & _LC110 & _LC119 & !x2 # !_LC103 & !_LC110 & !_LC119 & !_LC125 & x2 & x3 & y2 & y3 # !_LC103 & _LC110 & !_LC119 & !_LC125 & x3 & y2 & !y3 # !_LC103 & _LC110 & !_LC119 & !_LC125 & !x2 & x3 & y2; -- Node name is '|modulefull:24|74183:6|~7~4' = '|modulefull:24|74183:6|1SUM~4' -- Equation name is '_LC122', type is buried -- synthesized logic cell _LC122 = LCELL( _EQ044 $ GND); _EQ044 = _LC103 & _LC110 & x2 & x3 & y2 & y3 # _LC110 & _LC125 & x2 & x3 & y2 & y3 # _LC110 & _LC119 & x2 & x3 & y2 & y3 # _LC103 & !_LC110 & x3 & y2 & !y3 # _LC103 & !_LC110 & !x2 & x3 & y2; -- Node name is '|modulefull:24|74183:6|~7~5' = '|modulefull:24|74183:6|1SUM~5' -- Equation name is '_LC121', type is buried -- synthesized logic cell _LC121 = LCELL( _EQ045 $ GND); _EQ045 = !_LC110 & _LC125 & x3 & y2 & !y3 # !_LC110 & _LC125 & !x2 & x3 & y2 # !_LC110 & _LC119 & x3 & y2 & !y3 # !_LC110 & _LC119 & !x2 & x3 & y2; -- Node name is '|modulefull:24|74183:6|~8~1' -- Equation name is '_LC081', type is buried -- synthesized logic cell _LC081 = LCELL( _EQ046 $ VCC); _EQ046 = !_LC113 & !_LC114 & !_LC116 & !_LC118; -- Shareable expanders that are duplicated in multiple LABs: -- (none) Project Information d:\s3g15\lab5\parallel\lab5.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Standard Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'MAX7000S' family DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on PARALLEL_EXPANDERS = off REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SOFT_BUFFER_INSERTION = on SUBFACTOR_EXTRACTION = on TURBO_BIT = on XOR_SYNTHESIS = on IGNORE_SOFT_BUFFERS = off USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off One-Hot State Machine Encoding = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = on Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:00 Logic Synthesizer 00:00:03 Partitioner 00:00:00 Fitter 00:00:00 Timing SNF Extractor 00:00:01 Assembler 00:00:02 -------------------------- -------- Total Time 00:00:06 Memory Allocated ----------------- Peak memory allocated during compilation = 3,511K